
IDT82V3355
SYNCHRONOUS ETHERNET WAN PLL
Pin Description
15
May 19, 2009
JTAG (per IEEE 1149.1)
TRST
37
I
pull-down
CMOS
TRST: JTAG Test Reset (Active Low)
A low signal on this pin resets the JTAG test port.
This pin should be connected to ground when JTAG is not used.
TMS
41
I
pull-up
CMOS
TMS: JTAG Test Mode Select
The signal on this pin controls the JTAG test performance and is sampled on the rising edge
of TCK.
TCK
49
I
pull-down
CMOS
TCK: JTAG Test Clock
The clock for the JTAG test is input on this pin. TDI and TMS are sampled on the rising edge
of TCK and TDO is updated on the falling edge of TCK.
If TCK is idle at a low level, all stored-state devices contained in the test logic will indefinitely
retain their state.
TDI
51
I
pull-up
CMOS
TDI: JTAG Test Data Input
The test data is input on this pin. It is clocked into the device on the rising edge of TCK.
TDO
50
O
CMOS
TDO: JTAG Test Data Output
The test data is output on this pin. It is clocked out of the device on the falling edge of TCK.
TDO pin outputs a high impedance signal except during the process of data scanning.
This pin can indicate the interrupt of T0 selected input clock fail, as determined by the
Power & Ground
VDDD1
VDDD2
VDDD3
VDDD4
VDDD5
VDDD6
8
12
9
32
36, 38, 39, 45, 46
54
Power
-
VDDDn: 3.3 V Digital Power Supply
Each VDDDn should be paralleled with ground through a 0.1 F capacitor.
VDDA1
VDDA2
VDDA3
4
14
57
Power
-
VDDAn: 3.3 V Analog Power Supply
Each VDDAn should be paralleled with ground through a 0.1 F capacitor.
VDD_DIFF
22
Power
-
VDD_DIFF: 3.3 V Power Supply for OUT1
DGND1
DGND2
DGND3
DGND4
DGND5
DGND6
7
11
10
31
40
53
Ground
-
DGNDn: Digital Ground
Table 1: Pin Description (Continued)
Name
Pin No.
I/O
Type
Description 1